Yann LeCun   @ylecun   6/10/2021       

Very nice work from Google on deep RL- based optimization for chip layout. Simulated annealing and its heirs are finally dethroned after 40 years. This uses graph NN and deConvNets, among other things. I did not imagined back in the 90s that (de)ConvNets could be used for this.

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Posted by Yann LeCun